This Janus Henderson note by Richard Clode, CFA examines why a more consolidated and cautious semiconductor supply chain may curb AI-capex exuberance and reduce boom–bust risk.
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Industry consolidation has tightened control of key inputs: DRAM suppliers have fallen from 18 to 3, and TSMC dominates leading-edge foundry capacity, supporting greater supply discipline.
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Geopolitics and export restrictions (e.g., advanced lithography tools) limit China’s ability to supply cutting-edge compute/memory, reinforcing supply constraints.
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With ~3 years to build a new fab and estimates implying 3–5x capacity growth to meet forecasts, chipmakers may act as “adults in the room,” prioritising evidence-led expansion.
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